Semiconductor Memory Device, Electronic Card and Electronic Device

ABSTRACT

A semiconductor memory device comprises a cell array including bit lines arranged at a uniform pitch; and a plurality of bit line selection transistors connected to respective bit line ends for selectively connecting the bit line to a sense amp. The bit line selection transistors are translationally arrayed in a direction perpendicular to the bit line at an average array pitch greater than eight times the pitch of the bit lines.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2002-207383, filed on Jul. 16,2002; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and moreparticularly to an electrically erasable programmable non-volatilesemiconductor memory (EEPROM) having bit line selection transistorsarranged at a cell array end.

2. Description of the Related Art

In a mass NAND-type EEPROM configuration, bit lines arranged at a finepitch are divided into odd and even ones, and either one of them isselectively connected to a sense amp. In this case, bit line selectiontransistors are arranged in a cell array at bit line ends to select oddand even bit lines.

FIG. 13 shows a configuration covering from a cell array 1 to a senseamp 2 in such the NAND-type EEPROM, focusing attention on odd bit linesBLo (BLo0<k>-BLo7<k>) and adjacent even bit lines BLe (BLe0<k>-BLe7<k>).There is an arrangement region 3 for bit line selection transistorsQ0-Q15 between the cell array 1 and the sense amp 2. The cell array 1comprises NAND cell units U arrayed. Each unit includes plural (16 inthe shown example) non-volatile memory cells MC0-MC15 seriallyconnected. Each NAND cell unit U has one end connected to the bit lineBLo or BLe via a selection transistor S1 and the other end connected toa common source line CELSRC via a selection transistor S2.

The memory cells MC0-MC15 have control gates respectively connected toword lines WL0-WL15, which are arranged to intersect the bit lines BLoand BLe. The selection transistors S1 and S2 have gates connected toselection gate lines SGD and SGS, which are arranged in parallel withthe word lines. The ends of the bit lines BLo and BLe in the cell arrayare connected, via the bit line selection transistors controllable byselection signals BLSo and BLSe, to common sensing bit lines SBL, whichare connected to the sense amp 2. For example, the bit lines BLo0<k> andBLe0<k> are connected via the bit line selection transistors Q0 and Q1to the common sensing bit line SBL0<k>.

The bit line selection transistors Q0-Q15 are required to consist of ahigh voltage transistor because a high erasing voltage is applied to thebit line during data erase. This situation is specifically described.When data is written in the NAND-type EEPROM, the p-type well is held at0V and a write voltage of approximately 20V is applied to the selectedword line to inject electrons from the channel region into the floatinggate of the selected memory cell. This results in a higher threshold ofthe memory cell in a written state (for example, the state of “0” data).On the other hand, data is erased in a block batch of cells sharing thep-type well. During data erase, while all word lines in the cell blockare held at 0V and the bit lines are floated, an erase voltage ofapproximately 20V is applied to the p-type well to discharge the chargesfrom inside the floating gate of the memory cell to the substrate. Thisresults in a lower threshold of the memory cell in an erased state.

During data erase, the n-type diffusion layer connected to the bit lineis forward biased relative to the p-type well. Therefore, the erasevoltage of 20V may appear even on the floating bit line. The bit lineselection transistors are formed in another p-type well different fromthe p-type well in the cell array 1, and are isolated from the p-typewell in the cell array 1. When the voltage on the bit line is elevatedup to 20V, however, a junction breakdown may possibly arise between then-type source/drain diffusion layer of the bit line selection transistorand the p-type well, resulting in destruction of peripheral circuits.For the purpose of protection of the peripheral circuits, the bit lineselection transistor should consist of a high voltage transistor.

As described above, the need for the high-voltage bit line selectiontransistors may add constrains to downsize them. Therefore, when the bitlines are arranged at a much finer pitch in the cell array 1, the layoutof bit line selection transistors causes a problem.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of such thesituation and accordingly has an object to provide a semiconductormemory device capable of arranging bit line selection transistorswithout reduction of the area efficiency. An electronic card includingthe memory device mounted thereon is also provided, as well as anelectronic device utilizing the electronic card.

An aspect of the semiconductor memory device according to the presentinvention comprises a cell array including bit lines arranged at auniform pitch; and a plurality of bit line selection transistorsconnected to respective bit line ends for selectively connecting the bitline to a sense amp. The bit line selection transistors aretranslationally arrayed in a direction perpendicular to the bit line atan average array pitch greater than eight times the pitch of the bitlines.

Another aspect of the semiconductor memory device according to thepresent invention comprises a cell array including bit lines arranged ata uniform pitch; and a plurality of bit line selection transistorsconnected to respective bit line ends for selectively connecting the bitline to a sense amp. The bit line selection transistors aretranslationally arrayed in a direction perpendicular to the bit line atan average array pitch deviated from an integer multiple of the pitch ofthe bit lines.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more fully understood from the followingdetailed description with reference to the accompanying drawings, inwhich:

FIG. 1 shows a layout of bit line selection transistors according to anembodiment of the present invention;

FIG. 2 shows a layout of bit line selection transistors according toanother embodiment;

FIG. 3 shows a transistor block B0 in FIG. 2 and its wiring layout;

FIG. 4 shows a transistor block B1 in FIG. 2 and its wiring layout;

FIG. 5 shows a transistor block B2 in FIG. 2 and its wiring layout;

FIG. 6 shows a transistor block B3 in FIG. 2 and its wiring layout;

FIG. 7 shows a transistor block B4 in FIG. 2 and its wiring layout;

FIG. 8 shows a layout of bit line selection transistors according toanother embodiment;

FIG. 9 shows a layout of bit line selection transistors according toanother embodiment;

FIG. 10 shows another embodiment applied to a digital still camera;

FIG. 11 shows the internal configuration of the digital still camera;

FIGS. 12A to 12J show other electronic devices to which the embodimentis applied;

FIG. 13 shows a cell array arrangement in a NAND-type EEPROM in the art;and

FIG. 14 shows a layout of bit line selection transistors in a NAND-typeEEPROM of a comparative example.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A NAND-type EEPROM according to an embodiment of the present inventionwill be described below with reference to the drawings. This EEPROMincludes a cell array similar to the cell array 1 in FIG. 13. As shownin FIG. 13, the cell array 1 has a matrix arrangement that includesplural (16 in the shown example) non-volatile memory cells MC0-MC15serially connected to form a NAND cell unit. U, each pair of adjacentcells sharing a common source/drain diffusion layer. Each NAND cell unitU has one end connected to the bit line BLo or BLe via the selectiontransistor S1 and the other end connected to the common source lineCELSRC via the selection transistor S2. The memory cells MC0-MC15 haverespective control gates connected to the word lines WL0-WL15 that arearranged to intersect the bit lines BLo, BLe. The selection transistorS1, S2 have respective gates connected to the selection gate lines SGD,SGS that are arranged in parallel with the word lines.

To facilitate understanding of the layout of bit line selectiontransistors according to the embodiment of the invention, a comparativeexample is described first. FIG. 14 shows an arrangement region 3 forthe bit line selection transistors when data input/output is executed onan 8-bit basis at a certain column address <k>. Specifically, it is anexemplary layout showing a total of 16 bit lines including 8 odd and 8even bit lines, BLo0<k>, BLe0<k>, BLo7<k>, BLe7<k>; and thecorresponding 16 bit line selection transistors Q1-Q15. As shown, thebit line selection transistors are arranged in 2 rows of 8 stages in thebit line direction, each pair of adjacent transistors corresponding toodd and even bit lines, sharing a source/drain diffusion layer. In otherwords, 8 transistors are arranged in the bit line direction and 2 in adirection intersecting thereto. The bit line selection transistors havegates (hatched) that are continuously patterned in the directionintersecting the bit line for receiving the selection signals BLSo,BLSe.

The bit line selection transistors on B stages are arranged at a pitchcorresponding to 8 bit lines, b (=8a), where a defines a bit line pitch.For each pair of transistors sharing a common diffusion layer, thecommon diffusion layer is connected to the respective one of sensing bitlines SBL0-SBL7. From the bit line selection transistors in 8 stages×2rows, 8 sensing bit lines SBL0<k>-SBL7<k> are led out and connected to 8sense amps S/A0-S/A7. These 8 sense amps S/A0-S/A7 provide 8-bit data,which is input/output via I/O buffers simultaneously at one columnaddress.

In the layout of FIG. 14, if the bit line pitch a is further finelypatterned, the array pitch of the bit line selection transistors, b=8a,hardly isolates the bit line selection transistors from one anotherreliably. To the contrary, it can be considered that the bit lineselection transistors may have an array pitch of b=16a corresponding to16 bit lines. In this case, the bit line selection transistors arearranged in one row of 16 stages for 16 bit lines. This arrangementresults in a longer period, however, than that required for arrangementof the bit line selection transistors and extremely lowers the chip areaefficient.

On the other hand, FIG. 1 shows a layout of bit line selectiontransistors in the NAND-type EEPROM according to the embodiment. Asshown in the comparative example, the odd and even bit lines BLo, BLe inthe cell array are arrayed at the pitch a, and the bit line selectiontransistors are arranged at the bit line ends in 2 rows of 8 stages for16 bit lines. To the contrary, FIG. 1 shows an exemplary arrangement of20 bit lines (20BLs) in 10 stages×2 rows. The total number of bit linesis generally equal to an integer multiple of 16, or 16n. As is in theembodiment, if the total number of bit lines is equal to 80n, the bitline selection transistors may be arranged in 10 stages×8 rows for every80 bit lines (20BLs×4) as shown. The arrangement in n stages×m rows (n,m are integers of 2 or more), such as 10 stages×8 rows, is called atranslation arrangement.

This arrangement of the bit line selection transistors is characterizedby an average array pitch equal to the bit line pitch multiplied by aninteger other than a power of 2 while they are generally arranged at apitch equal to the bit line pitch multiplied by a power of 2 (forexample, 8 times).

The bit line selection transistors are formed in pairs of 2 stages (Q0,Q1), (Q2, Q3), . . . (Q14, Q15), each connected to odd and even bitlines adjacent in the bit line direction, sharing a source/draindiffusion layer. In the bit line selection transistors, a channel widthW direction (or gate width direction) is laid out to correspond to adirection perpendicular to the bit line.

For the bit line selection transistors arranged in the directionperpendicular to the bit line, their gates are formed as common gatelines 11 o, 11 e to receive the odd and even bit line selection signalsBLSo, BLSe.

In the bit line selection transistors, the array pitch b in the gatewidth W direction (or gate line direction) may be determined as b=10 a.For the bit line selection transistors in 10 stages×8 rows, 16transistors are required for every 16 bit lines. As shown, the bit lineselection transistors are arranged in 5 blocks of 16 transistors, B0-B4,within a range of 80 bit lines. A sense amp row 12 comprises sense ampgroups S/A<0>-S/A<4> arranged respectively corresponding to the blocksB0-B4.

Each sense amp group includes 8 sense amps. Connected to each sense ampgroup are 8 sensing bit lines, which are led out of the commonsource/drain diffusion layers in 16 bit line selection transistorsQ0-Q15.

In the example shown in FIG. 1, the total number of the bit lines isequal to an integer multiple of 80, which is the least common multipleassociated with 16 and 10. In this case, the bit line selectiontransistors may be arranged in 10 stages×8n rows, as described above. Inaddition, the bit line selection transistors may have an array pitch ofb=10a. If the total number of the bit lines is not equal to an integermultiple of 80, however, it is generally required to interweave the bitline selection transistors at portions having the number of the stagesdifferent from 10 stages.

FIG. 2 shows a layout of the bit line selection transistors, when thetotal number of the bit lines is equal to 80n+16, corresponding toFIG. 1. In this case, 80n indicates the number of the bit lines arrangedin a region R1, and 16 in a region R2. As previously described, withinthe range for 80n bit lines, the bit line selection transistors can bearranged in 10 stages×2 rows for every 20 bit lines. As for theremaining 16 bit lines, they may be arranged in 8 stages×2 rows. In thiscase, the array pitch b of the bit line selection transistors in thegate width W direction may be constant over the whole but is notrequired to be constant. For example, the bit line selection transistorsmay be arranged in the direction perpendicular to the bit line at two ormore different array pitches. As shown in FIG. 2, in the region R1 forevery 20 bit lines, an average transistor array pitch is represented byb1=10a−α/4n, and in the region R2 for 16 bit lines, it is represented byb2=8a+α. The bit line selection transistors have an average array pitchof b, which is represented by (the number of bit lines×a)/the number oftransistors. Accordingly, b=(80 n+16)a/(8n+2)=10 a−2a/(4 n+1). In aword, the average array pitch of the bit line selection transistors inthe direction perpendicular to the bit line is equal to a value deviatedfrom an integer multiple of the bit line pitch a.

FIGS. 3-7 more specifically show the layout of the bit line selectiontransistors in FIG. 2 or FIG. 1, including wiring portions, in therespective blocks B0-B4 for every 16 bit lines of the 80 bit lines.FIGS. 3, 4, 5, 6 and 7 focus attention on B0, B1, B2, B3 and B4 in FIGS.1 and 2, respectively. These blocks B0-B4 correspond to respectivecolumn addresses <0>-<4> to input/output 8-bit data at one columnaddress. In each block, the corresponding sense amp group is located.For example, the sense amp group S/A<0> is located in the block B0. Thesense amp group includes 8 sense amps.

As shown in FIGS. 3-7, the bit line BLo, BLe is extended and wired fromthe cell array region to the region of the bit line selection transistorto be connected, and connected to the corresponding source/draindiffusion layer using a lateral wire 13 shown by the dashed line. Thelateral wire 13 is a metal wire in a different layer from the bit lineBLo, BLe. In relation to the group of 8 sense amps, S/A, the sensing bitlines SBL0-7 are arranged in parallel with the bit lines BLo, BLe in thecell array. They are each connected to a common diffusion layer betweena pair of transistors via a lateral wire shown by the dashed line.

In the example shown in FIG. 2, the total number of the bit lines isequal to 80n+16. Alternatively, the total number of the bit lines may beequal to 80n+32, 80n+48, or 80n+64, for example. In these cases, it isalso required to interweave the bit line selection transistors atportions having the number of the stages different from 10 stages. In anexample shown in FIG. 8, the total number of the bit lines is equal to80n+48. In this case, 80n indicates the number of the bit lines arrangedin a region R3, and 48 in a region R4. As for the section of the 80n bitlines, except for a delicate deviation in the pitch of the bit linesection from that of the transistor section, the bit line selectiontransistors may be arranged in 10 stages×8n rows as explained in FIG. 1.As for the section of the remaining 48 bit lines, the transistors may bearranged in 10 stages×4 rows+one row of 8 stages as shown in FIG. 8. Inthis case, the array pitch b of the bit line selection transistors inthe gate width direction is represented by b=(80n+48)a/(8n+5)=10a−2a/(8n+5) on average.

Similarly, if the total number of the bit lines is equal to 80n+32, notshown, the transistors are arranged in 10 stages×8n rows+8 stages×4rows. In this case, the array pitch b of the bit line selectiontransistors in the gate width direction is represented byb=10a−2a/(2n+1) on average. If the total number of the bit lines isequal to 80n+64, the transistors are arranged in 10 stages×(8n+4) rows+8stages×3 rows. In this case, the array pitch b of the bit line selectiontransistors in the gate width direction is represented byb=10a−6a/(8n+7) on average.

In summary, according to this embodiment, the array pitch of the bitline selection transistors in the direction perpendicular to the bitline is more than 8 bit lines and less than 10 bit lines on average.Therefore, this average array pitch of the transistors can be determinedto have a value deviated from 10 times or an integer multiple of the bitline pitch. In this case, even if the bit line selection transistors cannot be contained within a period of 8 bit lines, they can be arrangedwith margins. In addition, any useless area is not required as is in thearrangement in a period of 16 bit lines. A higher chip area efficiencycan be expected while the transistor arrangement is forced to partiallydiffer in number of stages.

In the preceding embodiments, the pair of the bit line selectiontransistors connected to the adjacent odd and even bit lines BLo, BLeare laid out to align parallel with the bit line direction. To thecontrary, if the transistors are rotated by 90°, the pair of the bitline selection transistors connected to the adjacent odd and even bitlines BLo, BLe may be laid out to align parallel with the directionperpendicular to the bit line direction.

In other words, the gate length direction intersects the bit line atright angle. A layout of the bit line selection transistors in such anembodiment is shown in FIG. 9.

In the example shown in FIG. 9, the width in the gate length directionof the transistor pair can fall within 40 bit lines.

If the total number of the bit lines is equal to an integer multiple of40, transistor pairs of 20 stages can be arranged within the width of 40bit lines, b1 (=40a).

This is effective to lay out the bit line selection transistors withoutany useless area. In the example shown in FIG. 9, however, the totalnumber of the bit lines is represented by a sum of an integer multipleof 40 and an integer multiple of 42. In this case, transistor pairs of21 stages are arranged within the width of 40 bit lines, b2 (=42a). As aresult, the array pitch of the bit line selection transistors in thedirection orthogonal to the bit line is determined to have an averagelarger than b1 and smaller than b2.

The bit lines BLo, BLe and the sensing bit lines SBL can be connected tothe corresponding transistor diffusion layers using the lateralintersection wires shown with the dashed lines similar to the precedingembodiments.

Also in this embodiment, the transistor arrangement can be achieved withimproved area efficiency while the bit line selection transistorspartially differ in number of stages in the bit line direction.

In the examples described in the above embodiments, the sense amps arearranged only at one end of the bit lines. As the bit line pitch is muchmore finely patterned, the sense amps are often hardly arranged in suchthe manner. In such the case, it is effective to divide 8 I/Os into twoand arrange each 4 I/Os at each of both ends of the bit lines, forexample.

As described above, according to the embodiments of the invention, it ispossible to provide a semiconductor memory device capable of arrangingbit line selection transistors without reduction of the area efficiency.

As an embodiment, an electronic card using the non-volatilesemiconductor memory devices according to the above-describedembodiments of the present invention and an electronic device using thecard will be described bellow.

FIG. 10 shows an electronic card according to this embodiment and anarrangement of an electronic device using this card. This electronicdevice is a digital still camera 101 as an exemplary portable electronicdevice. The electronic card is a memory card 51 used as a recordingmedium in the digital still camera 101. The memory card 51 incorporatesan IC package PK1 in which the non-volatile semiconductor memory deviceor the memory system according to the above-described embodiments isintegrated or encapsulated.

The case of the digital still camera 101 accommodates a card slot 102and a circuit board (not shown) connected to this card slot 102. Thememory card 51 is detachably inserted into the card slot 102 of thedigital still camera 101. When inserted into the slot 102, the memorycard 51 is electrically connected to electric circuits on the circuitboard.

If this electronic card is a non-contact type IC card, it iselectrically linked to the electric circuits on the circuit board viaradio signals when inserted into or approached to the card slot 102.

FIG. 11 shows a basic arrangement of the digital still camera. Lightfrom an object is converged through a lens 103 and input to an imagepickup device 104. The image pickup device 104 is, for example, a CMOSsensor and photoelectrically converts the input light to output, forexample, an analog signal. This analog signal is amplified at an analogamplifier (AMP), and converted into a digital signal at an A/D converter(A/D). The converted signal is input to a camera signal processingcircuit 105 where the signal is subjected to automatic exposure control(AE), automatic white balance control (AWB), color separation, and thelike, and converted into a luminance signal and color differencesignals.

To monitor the image, the output signal from the camera processingcircuit 105 is input to a video signal processing circuit 106 andconverted into a video signal. The system of the video signal is, e.g.,of the NTSC (National Television System Committee). The video signal isinput to a display 108 attached to the digital still camera 101 via adisplay signal processing circuit 107. The display 108 is e.g., a liquidcrystal monitor.

The video signal is supplied to a video output terminal 110 via a videodriver 109. An image picked up by the digital still camera 101 can beoutput to an image apparatus such as a television set via the videooutput terminal 110. This allows the picked-up image to be displayed onan image apparatus other than the display 108. A microcomputer 111controls the image pickup device 104, the analog amplifier (AMP), theA/D converter (A/D), and the camera signal processing circuit 105.

To capture an image, an operator presses an operation button such as ashutter button 112. In response to this operation, the microcomputer 111controls a memory controller 113 to write the output signal from thecamera signal processing circuit 105 into a video memory 114 as a frameimage. The frame image written in the video memory 114 is compressed onthe basis of a predetermined compression format by acompressing/stretching circuit 115. The compressed image is recorded,via a card interface 116, in the memory card 51 inserted into the cardslot.

To reproduce a recorded image, an image recorded on the memory card 51is read out via the card interface 116, stretched by thecompressing/stretching circuit 115, and written into the video memory114. The written image is input to the video signal processing circuit106 and displayed on the display 108 or another image apparatus in thesame manner as the image is monitored.

In this arrangement, those mounted on the circuit board 100 include thecard slot 102, the image pickup device 104, the analog amplifier (AMP),the A/D converter (A/D), the camera signal processing circuit 105, thevideo signal processing circuit 106, the display signal processingcircuit 107, the video driver 109, the microcomputer 111, the memorycontroller 113, the video memory 114, the compressing/stretching circuit115, and the card interface 116.

The card slot 102 is not required being mounted on the circuit board100, and can also be connected to the circuit board 100 via a connectorcable or the like.

A power circuit 117 is also mounted on the circuit board 100. The powercircuit 117 receives power from an external power source or battery andgenerates an internal source voltage for use in the digital still camera101. For example, a DC-DC converter can be used as the power circuit117. The internal source voltage is supplied to the various circuitsdescribed above, in addition to a strobe 118 and the display 108.

As described above, the electronic card according to this embodiment canbe used in portable electronic devices such as the digital still cameraexplained above. However, the electronic card can also be used invarious apparatus such as those shown in FIGS. 12A to 12J, as well as inportable electronic devices. That is, the electronic card can also beused in a video camera shown in FIG. 12A, a television set shown in FIG.12B, an audio device shown in FIG. 12C, a game machine shown in FIG.12D, an electronic musical instrument shown in FIG. 12E, a cell phoneshown in FIG. 12F, a personal computer shown in FIG. 12G, a personaldigital assistant (PDA) shown in FIG. 12H, a voice recorder shown inFIG. 12I, and a PC card shown in FIG. 12J.

The aforementioned embodiments are merely examples and hence do notrestrict the present invention. Although a NAND-type flash memory deviceis explained in the above-described embodiments, the present inventionis applicable to, for example, a NOR-type, a DINOR-type, and the likenon-volatile semiconductor memory devices.

While the present invention has been particularly shown and describedwith reference to the embodiments, it will be understood by thoseskilled in the art that various changes in form and detail may be madewithout departing from the spirit, scope, and teachings of theinvention.

1. A semiconductor memory device, comprising: a cell array including bitlines arranged at a uniform pitch; and a plurality of bit line selectiontransistors connected to respective bit lines ends for selectivelyconnecting said bit line to a sense amp, wherein said bit line selectiontransistors are translationally arrayed in a direction perpendicular tosaid bit line at an average array pitch greater than eight times saidpitch of said bit lines. 2-23. (canceled)